1. Field of the Invention
The present invention relates to a ROM memory matrix or memory array.
2. Discussion of the Related Art
FIG. 1 generally shows the structure of a ROM matrix. This matrix comprises a set of rows or word lines Li crossing columns or bit lines Cj. At each crossing of a row Li and a column Cj, a transistor Tij is placed, having its gate connected to a line Li, its drain to a column Cj and its source to a reference potential Vss, for example, the ground.
The memory matrix is programmed upon fabrication, so that there exists or not a transistor Tij at each crossing point. For reasons of simplicity of fabrication and charge balancing, a transistor Tij is generally placed at each crossing point and the transistors located at the crossing points which are desired to be inactive are inhibited, for example, by inhibiting their gate, or by not implementing their drain connection.
This matrix structure is associated with several circuits for decoding rows or word lines and columns or bit lines, precharge, amplification, multiplexing, etc. These various circuits, which are known and are not per se the object of the present invention, will not be described herein.
FIG. 2 very schematically shows a cross-sectional view along a column of a basic structure implementing the memory array of FIG. 1 Each transistor Tij is formed in a lightly-doped semiconductor substrate 10 of a first conductivity type, and is separated from its neighbors by a thick oxide region 11. Gate G of this MOS transistor corresponds to a portion of a conductive line Li, for example, in polysilicon, covering all the gates of the MOS transistors in a same row and extending, between the transistors, above the thick oxide regions. The sources S of all the transistors in a same row correspond to a portion of a continuous diffused row connected to potential Vss (there is no thick oxide between the sources of adjacent transistors in a same row). All the drains D of the transistors of a column are connected to a same column metallization Cj through vias 12.
The diagram of FIG. 2 is extremely simplified and, in practical implementations, various modifications are made. For example, the drains and sources are of LDD-type, a threshold adjustment doping is performed under the gates, the gate polysilicon is coated with a metal silicide, several levels of polysilicon exist, several levels of metallization exist . . .
Anyway, the successive steps of fabrication of an integrated circuit incorporating a ROM array sequentially include the following main steps:
forming a pre-array, PA1 forming a thick oxide, PA1 forming a first level of polysilicon, PA1 forming diffused areas, PA1 forming several levels of metallization.
Generally, in the semiconductor industry, the technical operations implemented in the silicon (Front End) are clearly separated from the operations relative to forming metallizations and vias (Back End). These two types of operations are performed in different sections of a same array, or even in different array.
From a practical point of view, it is interesting to postpone the steps of programming a memory array (determining the active and inactive transistors) to the Back End steps. Thus, an intermediary component including all the diffusions in the silicon, at the level of the memory array as well as at the level of the other components, for example, a processor, implemented in the same integrated circuit, can be prefabricated and stored to program the ROM array by the metallizations upon arrival of a customer order, which enables to achieve much faster supply times.
As previously indicated, there are several techniques for inhibiting selected crossing points.
A first family of techniques consists of inhibiting the transistor gates. This can be done by leaving a thick oxide at the location where the thin gate oxide would have been formed. This technique has the disadvantage that the programming of the memory array has to be done at the first fabrication step. Another technique consists of implementing arrays under the gate to highly dope the substrate and thus make the gate action inoperative. This other technique has the disadvantage of being complex and adding a fabrication step with respect to usual processes, and also of being implemented in the Front End steps.
However, these gate programming techniques have the advantage of enabling to considerably increase the integration density with respect to the basic structure illustrated in FIG. 1.
This is illustrated in FIG. 3 which shows a memory array implemented so that each pair of word lines shares a same reference row Vss (in the example, between rows Li-2 and Li-1 and between rows Li and Li+1). This means that each pair of adjacent transistors of a same row shares a same source. Similarly, the drains of two adjacent transistors, for example between lines Li-1 and Li, are common. The advantage of this structure is that the rows of thick oxide are suppressed between transistor rows and the number of drains and sources is divided by 2. Clearly, as a result, there is a very significant size reduction of the memory array with respect to the basic diagram of FIG. 1.
A second important family of techniques consists of implementing or not the connections between a column metallization and individual drains. For this purpose, as shown in FIG. 2, it should be noted that it is enough to suppress some of vias 12. The programming can thus be performed by a contact etching mask (which may be implemented between two upper metallization layers and not under a lower metallization layer as shown in the drawing). This type of technique has the advantage that the programming of the ROM can be performed at the Back End steps.
However, these techniques have the disadvantage that it is no longer possible, as in the diagram of FIG. 3, to provide a structure in which adjacent transistors have a common drain. It is then necessary to use memory array configurations of the type shown in FIG. 4 where adjacent transistors do have a common source but have separated drains, that is, there will be a FIG. 4. Thus, with respect to the basic structure of FIG. 1, the size is reduced by suppressing one source diffusion out of two and the intermediary thick oxide between these sources, but all drain diffusions and the thick oxides separating these drain regions are maintained.
Thus, in the current state of the art, one practically has to choose between privileging either the compactness of a memory array by selecting a gate programming technique, at the cost of fabrication convenience, or fabrication convenience by selecting a drain programming technique at the cost of compactness.